FPGA Development and Evaluation Board
by Department of Higher Education
Published
Tue, 29 Sept
3:37 pm
Bid submission closes
Tue, 20 Oct
4:00 pm· 20 days left
Key terms of this bid
Read from the GeM bid document on 30 Sept 2026, 3:30 am IST. The document below is the final word.
- EMD
- Not required
- Performance security
- Not required
- Minimum turnover
- ₹4,00,000
- 4 lakh a year, average of 3 years
- Experience
- 3 years
- Of similar supply or service
- Past performance
- 30%
- Of bid quantity supplied before
- Bid type
- Two Packet
- Total value wise evaluation
- Reverse auction
- No
- Offer validity
- 180 days
- From the bid end date
- Experience & turnover relaxation
- No
- Purchase preference
- MSE + Make in India
Documents sellers must upload
- Experience Criteria
- Past Performance
- Bidder Turnover
- Certificate (Requested in ATC)
- OEM Authorization Certificate
- OEM Annual Turnover
- Additional Doc 1 (Requested in ATC)
- Compliance of BoQ specification and supporting document
Delivery location
National Institute of Technology Calicut,nit campus p o,Chathamangalam
PIN 673601 · Quantity 2 · Deliver within 30 days
Tender details
- Organisation
- Ministry of Education › Department of Higher Education
- Location
- Central Government
- Tender ID
- GEM/2026/B/8071124
- Category
- IT & Electronics
- Quantity
- 2
- Source portal
- GeM — Government e-Marketplace
Bid document
How to bid
- 1Read the bid document on this page: the terms, eligibility, EMD, specifications and ATC (additional terms and conditions).
- 2Log in to your GeM seller account (register at gem.gov.in if you don't have one; it's free).
- 3Search BidPlus for bid number GEM/2026/B/8071124 and submit your offer before the closing time.
New to bidding? Read GeM seller registration: documents, charges and steps, How to read a GeM bid document, section by section and GeM reverse auction: how bid to RA works, who gets in and how L1 is decided.
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